Slice Analysis Based Bayesian Power Model for Sequential Circuits ∗

Bayesian modeling method and slice analysis techniques show good effect in cycle-accurate power analysis of combinational circuit. In this paper, we use virtual signal logical depth assignment to resolve the problem that signal loop can not be sliced in sequential circuits. With this method, we build cycle-accurate power model based on Bayesian inference and slice analysis techniques. The experiments on ISCAS89 benchmark show that the power-per-cycle estimation error is 6.7%. By analyzing the relation between error trend under different slices and circuit’s size, we also build a thumb rule about how to choose best slice number: when the accumulative gate number is about 73% of total gate number, the model error with slice-based parameters usually arrives minimum value.